The present invention relates to stacked microelectronic assemblies, to methods of forming such assemblies, and to components useful in such assemblies.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a relatively expansive front face having contacts connected to the internal circuitry of the chip. Each individual chip is mounted in a package, which in turn is connected to a circuit panel, such as a printed circuit board, so that the contacts of the chip are connected to conductors of the circuit panel. In “flip-chip” designs, the front face of the chip faces the circuit panel, and the contacts on the chip are connected to the circuit panel by solder balls or other connecting elements. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself.
As disclosed, for example, in certain embodiments of commonly assigned U.S. Pat. Nos. 5,148,265, 5,148,266 and 5,679,977, the disclosures of which are hereby incorporated by reference herein, certain innovative mounting techniques offer compact assemblies with good reliability and testing approaches. A package which can accommodate a single chip in an area of the circuit panel equal to or slightly larger than the area of the chip itself is commonly referred to as a “chip-size package”.
The total area of a plurality of chips mounted on a circuit panel is also a concern. Various proposals have been advanced for providing plural chips in a single package or module. It has been proposed to package plural chips in a “stacked” arrangement, i.e., an arrangement where chips are placed one on top of another. In a stacked arrangement, several chips can be mounted in an area of the circuit panel that is less than the total area of the chips. Certain stacked chip arrangements are disclosed, for example, in certain embodiments of the aforementioned '977 and '265 patents and in U.S. Pat. No. 5,347,159, the disclosures of which are hereby incorporated by reference herein. U.S. Pat. No. 4,941,033, also hereby incorporated by reference herein, discloses an arrangement in which chips are stacked one on top of another and interconnected with one another by conductors on so-called “wiring films” associated with the chips.
Still further improvements in stacked chip assemblies, for incorporating other elements within the assembly, would be desirable.